置位复位触发器
Design and Analysis of SEU/ SET Hardened D Flip-Flop
SEU/SET加固D触发器的设计与分析
Calculation for the data resulted from simulation shows that power dissipation of the system adopting DET flip-flop can be reduced evidently because of using the clock with half working frequency, in comparison with its counterpart adopting SET flip-flop.
对模拟所得数据的计算结果表明,与采用相同功能的单边沿触发器的系统比较,由于工作频率减半可使采用双边沿触发器的系统功耗明显降低。
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